The present invention relates to a semiconductor memory device and more particularly to a memory device including a bit line equalizing circuit which can reduce the generation of substrate current and thus stabilize a substrate voltage.
As the semiconductor device has a tendency toward high integration, the number of sense amplifier and bit line equalizers also proportionally increases. The bit line equalizer makes potentials of a pair of bit lines BL and BL equal before that the potentials of the pair of bit lines BL and BL are amplified by the sense amplifier. Thus, when the voltages of the bit lines are amplified, data is detected by the potential change of the bit lines.
FIG. 1 is a circuit diagram of a conventional memory device. In FIG. 1, the conventional memory device comprises a bit line equalizer 10, a memory cell 20, and a sense amplifier 30. The bit line equalizer 10 is located between the bit lines BL and BL, where a voltage V.sub.BL is applied to the sources of NMOS transistors N1 and N2 for charging the bit lines BL and BL which are connected to their drains, respectively. Also, an NMOS transistor N3 is connected to the bit lines BL and BL with its source and drain in order to equalizer their potential to the bit line precharge voltage V.sub.BL which is conventionally half of a power supply voltage, that is, 1/2Vcc. A bit line equalizing control clock .phi.EQ is applied to gates of the NMOS transistors N1, N2 and N3. The memory cell 20 comprises two NMOS transistors N4 and N5, of which gates are connected to word lines WLn and WLn+1, sources are connected to capacitors C1 and C2 for storing cell data, and drains are connected to the bit lines BL and BL, respectively. The bit lines BL and BL are also connected to the sense amplifier 30.
FIG. 2 is a diagram illustrating operational waveforms of the conventional memory device as shown in FIG. 1. The bit lines BL and BL are respectively amplified to a ground voltage Vss and the power supply voltage Vcc by the sense amplifier 30 when a RAS(row address strobe) signal as shown in FIG. 2(A) is in a low level state. Next, if the RAS signal goes into a high level of nonactivation state, the bit line equalizing control clock .phi.EQ in a high level state as shown in FIG. 2(B) is applied to the gates of the NMOS transistors N1, N2 and N3 by a chip selector which is not shown in FIG. 1. Also, the word lines WLn and WLn+1 as shown in FIG. 2(C) become a low level state in a row address (not shown) before the bit line equalizing control clock .phi.EQ becomes a high level state.
Then, the NMOS transistors N4 and N5 in the memory cell 20 is turned off and thus the data stored in capacitors C1 and C2 are not discharged toward the bit lines BL and BL. Consequently, the bit lines BL and BL are equalized to the bit line precharge voltage V.sub.BL as shown in FIG. 2(D) and maintained on until next activation cycle.
At this time, the NMOS transistor N3 to equalize the bit lines BL and BL in the bit line equalizer 10 is turned on by the bit line equalizing control clock .phi.EQ after the supply voltage Vcc was applied between the source and the drain of the NMOS transistor N3 in such a manner that the source and the drain of the NMOS transistor N3 have different potentials in the power supply voltage Vcc thereof and the bit line equalizing control clock .phi.EQ applied to the gate of the NMOS transistor N3 is changed into the power supply voltage Vcc from the ground voltage Vss so as to generate the substrate current.
Also, according to the high integration tendency of the memory device, the numbers of memory cells, sense amplifiers, and bit line equalizers are also increased and the number of bit line equalizers which is operating for every activation cycle is also increased. Therefore, the amount of the substrate current which is produced during the operation of the bit line equalizers is increased and thus the substrate potential is largely changed, thereby weakening in the reliability of the memory device.